--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.proc_package.ALL;
use work.proc_components.ALL;

entity top is
	port (
		clk : in std_logic
		
		--- Add More I/O here
	);
end top;

architecture Behavioral of top is
	
	-- Internal Bus Routing
	signal bus_out : PROC_BUS_DATA_TYPE;
	signal bus_in : PROC_BUS_DATA_TYPE;
	signal bus_addr : PROC_BUS_ADDR_TYPE;
	signal bus_busy : std_logic;
	signal bus_rdwr : std_logic;
	signal bus_en : std_logic;
	signal bus_rst : std_logic;
	signal bus_clk : std_logic;
	
	-- Program Memory Port
	signal prog_mem_clk : std_logic;
	signal prog_mem_en : std_logic;
	-- Use top 0xFF addresses for Program Memory
	signal prog_mem_addr : std_logic_vector(8 downto 0);
	signal prog_mem_data : PROC_PROG_DATA_TYPE;
	
begin

	processor_0 : proc_top port map (
		-- Control
		clk => clk,
		rst => '0',
		en => '1',
		
		halt => '0',
		
		-- Debug Port
		debug_reg_addr => (others => '0'),
		debug_reg_wr_en => '0',
		debug_reg_in => (others => '0'),
		--debug_reg_out => ,
		--debug_pc_out => , -- uncomment and connect to use them
		--debug_instruction => ,
		
		-- External Bus
		bus_out => bus_out,
		bus_in => bus_in,
		bus_addr => bus_addr,
		bus_busy => bus_busy,
		bus_rdwr => bus_rdwr,
		bus_en => bus_en,
		bus_rst => bus_rst,
		bus_clk => bus_clk,
		
		-- External Program Memory
		prog_mem_clk => prog_mem_clk,
		prog_mem_en => prog_mem_en,
		prog_mem_addr => prog_mem_addr(7 downto 0),
		prog_mem_data => prog_mem_data
	);
	
	-- Use the Top 0xFF addresses only for Program Memory
	prog_mem_addr(8) <= '0';
	
	memory_0 : mem_block port map (
		-- Port A (Connected to Program Memory of Processor_0 (Read Only)
		a_clk => prog_mem_clk,
		a_en => prog_mem_en,
		a_wr_en => '0',
		a_addr => prog_mem_addr,
		a_in => (others => '0'),
		a_out => prog_mem_data,
		
		-- Port B
		b_clk => '0',
		b_en => '0',
		b_wr_en => '0',
		b_addr => (others => '0'),
		b_in => (others => '0')
		--b_out =>
	);
	
end Behavioral;

